RASSP Digest Theme: Model Year Architectures

To achieve the 4X time-to-market and life cycle cost improvement goals of the RASSP program, designers must focus not only on how they design, but on what they design as well. Lockheed Martin’s Advanced Technology Labs is developing a Model Year Architecture (MYA) that promotes design upgrades and reuse via standardized, open interfaces while leveraging state-of-theart commercial technology developments. This article describes one element of the MYA that supports interoperability, the Standard Virtual Interface. 1. Model Year Architecture Overview The basic framework for the Model Year Architecture was described in more detail in a previous article in the RASSP Digest (Vol. 2, 3Q95). Briefly, the MYA is a framework for reuse that provides a structured approach to ensure that designs incorporate the features required to promote upgradability. The basic elements that comprise the MYA are the Functional Architecture, Encapsulated Library Components, and Design Guidelines and Constraints, as shown in Figure 4 on page 24 of the last RASSP Digest (Vol. 2, 3rd Qtr.). Synergism between the Model Year Architecture Framework and the RASSP Methodology is required, as all areas of the methodology, including architecture development, hardware/software codesign, reuse library management, hardware synthesis, target software generation, and design for test are impacted by the MYA Framework. The Functional Architecture defines the necessary components, and their interfaces, to ensure that the design is upgradable and facilitates technology insertion. It is a starting point for developing solutions for an applicationspecific set of problems, not a detailed instantiation of an architecture. 2. Standard Virtual Interface The Standard Virtual Interface (SVI) defines a concept to facilitate interoperability and upgradability of various architectural level reuse library elements (such as processor nodes and interface elements) by defining a standard interface encapsulation procedure. In the past, integration of a processor to a specific interconnect has been performed as a specialized implementation; this point-topoint integration approach can lead to a total of N**2 possible integrations for N processors and interconnects. The intent of the SVI is to provide a common functional interface for all of these integrations, greatly reducing the number of integrations required. Thus, once a processor has been integrated to the SVI standard, it can be integrated to any interconnect integrated to this standard. This approach provides a level of plug and play interoperability that has not been realized in the past. Additionally, the SVI is a functional, not physical, interface specification that supports technology independence — hence, the use of the term virtual in SVI. Figure 1 illustrates an SVI implementation. In this example, a “PE” can be an element or cluster of elements connected as a single node to an interconnect. Examples of PEs include signal processors, vector processors, or shared memory. The term “interconnect” can be any interconnect fabric or network. Examples of interconnect fabrics include XBAR-based point-to-point interconnect networks, rings, and multidrop buses. Examples of networks include Ethernet, FDDI, Fiber Channel, 1553B, etc. Each library element (processor or interface) includes a hardware wrapper (encapsulation) which implements the SVI functions. During the hardware implementation, the logic described within the encapsulations from both sides of the SVI is combined and optimized wherever possible. This process may cause some of the signals defined for the SVI to become implicit in the remaining logic. In addition, what remains of the SVI is expected to be embedded within an ASIC, gate array, or FPGA, and would not appear as explicit pins on a chip or interface connector. The SVI definition is general enough to handle different interprocessor communication paradigms. Some interconnect networks support the message passing paradigm to communicate, while others support the global shared memory paradigm. Likewise,